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[Software Engineering] testbench

Description: ritting testbench 入门级的还有XILINX的一篇文档how to write a testbench。 你看看这个，看思想。-entry-level ritting testbench are XILINX a document how to write a testbench. You take a look at this, look at the ideological.
Platform: | Size: 2048 | Author: 老刘 | Hits:

[Embeded-SCM Develop] spartan3elab5

Description: 关于xilinx大学计划配需教程实验五源代码-Xilinx University plans with regard to the need tutorial experimental five-source code
Platform: | Size: 5323776 | Author: 小贝 | Hits:

[VHDL-FPGA-Verilog] Xilinx_sparten3E_communication_between_key_board_a

Description: 在Xilinx Spartan-3E的开发板中，实现键盘和VGA显示器的通信的源代码，与大家分享：-In the Xilinx Spartan-3E development board, the realization of the keyboard and VGA display the source code of communication to share with you:
Platform: | Size: 2048 | Author: lijq | Hits:

[VHDL-FPGA-Verilog] fifoi

Description: 基于Xilinx Vertex2的可综合的2048x10位的读写可控制FIFO模块源代码，深度可控-Based on the Xilinx Vertex2 can be integrated 2048x10-bit read and write can control the FIFO module source code, the depth of controllable
Platform: | Size: 2048 | Author: 云 | Hits:

[VHDL-FPGA-Verilog] ECCgenAndLoc

Description: 基于xilinx ISE环境开发的VHDL的NAND flash ECC 实现,eccGen256Byte 文件夹为ECC 产生程序，EccErrLoc文件夹为ECC错误定位程序。-Xilinx ISE environment based on the development of VHDL the NAND flash ECC to achieve, eccGen256Byte folder produced for the ECC procedures, EccErrLoc folder location for the ECC error procedures.
Platform: | Size: 1504256 | Author: 卓智海 | Hits:

[Com Port] uart

Description: 串口通讯rs232,时钟频率为40Mhz,波特率为19200,没有奇偶校验,在xilinx XC3S200A板子上验证过.-Serial communication rs232, clock frequency of 40Mhz, the baud rate to 19200, no parity, in the board on xilinx XC3S200A verified.
Platform: | Size: 6144 | Author: zhangjiansen | Hits:

[Other] multiper

Description: 用xilinx写的vhdl乘法器。是二进制的两位乘法器。里面含有代码和电路图。-Written in VHDL using Xilinx multiplier. Binary multiplier is two. Which contains code and circuit diagrams.
Platform: | Size: 113664 | Author: 费颖 | Hits:

[Other] DCM

Description: 关于dcm的教材。教你如何使用dcm。非常值得一看哦-Materials on the DCM. Teach you how to use the dcm. Oh, very much worth a visit
Platform: | Size: 621568 | Author: 刘峰 | Hits:

[VHDL-FPGA-Verilog] clock_module_ref

Description: Xilinx clock module design
Platform: | Size: 2048 | Author: Mingli | Hits:

[Com Port] pro104_uart

Description: uart的代码，经实际运行可以通信，是xilinx uart 代码的改进，网上的xilinx uart代码有很多bug，用此代码可以改进运行。-UART code, the actual operation can be communication, xilinx uart code are improved, xilinx uart code online has a lot of bug, the code can be improved with this operation.
Platform: | Size: 613376 | Author: max | Hits:

[VHDL-FPGA-Verilog] 11_vga

Description: This vga controller write in vhdl xilinx ise Connect your vga monitor and view many color in moniotr-This is vga controller write in vhdl xilinx ise Connect your vga monitor and view many color in moniotr
Platform: | Size: 6144 | Author: darek | Hits:

[Software Engineering] LibrariesGuide

Description:
Platform: | Size: 5925888 | Author: 雷杨杰 | Hits:

[VHDL-FPGA-Verilog] lab5

Description: VHDL xilinx例子-vhdl xilinx example............
Platform: | Size: 585728 | Author: hojone | Hits:

[VHDL-FPGA-Verilog] BUFG_CLK2X_FB_SUBM

Description: xilinx DCM 应用的源代码，完全可用-xilinx DCM application source code, fully available
Platform: | Size: 1024 | Author: 娃娃 | Hits:

[VHDL-FPGA-Verilog] DUC

Description: 基于XILINX ISE下的数字上变频设计，其中用到了XILINX的乘法IP。已经通过工程实用，好用。-XILINX ISE based on frequency of figure design, use one of the XILINX multiplication IP. Has passed the project practical, easy to use.
Platform: | Size: 18432 | Author: 咚咚 | Hits:

[VHDL-FPGA-Verilog] Simulation-and-FPGA-Implementation-of-DigitalDBPSK

Description: 文章介绍了系统的硬件电路原理与具体实现方法，其中主要包括载波恢 复电路，PN 码捕获电路和跟踪电路，并针对Xilinx 公司FPGA 的特点，对各电 路的实现进行优化设计，在不影响系统稳定性和精度的前提下，减少硬件资源 消耗，提高硬件利用率。设计利用Verilog 硬件描述语言完成，通过后仿真验证 电路正确性，并给出综合结果。-This paper introduces the system' s hardware circuit principle and the specific implementation methods, which mainly include the carrier recovery circuit, PN code acquisition circuit and track circuits, and FPGA for Xilinx company characteristics, the implementation of the circuit to optimize the design, without affecting the system stability and precision under the premise of reduced hardware resource consumption, improve hardware utilization. Designed using Verilog Hardware Description Language finish, after the passage of the correctness of circuit simulation, and give General results.
Platform: | Size: 1007616 | Author: mayuan | Hits:

[VHDL-FPGA-Verilog] pci_core.tar

Description: vhdl 写的 PCI IP核程序，已经过测试-pci ip core
Platform: | Size: 23552 | Author: planet1997 | Hits:

[Embeded-SCM Develop] fifo_core

Description: 经典的FIFO实现源码，里面有三种类型，是xilinx工程师写的，经典-Classic source FIFO implementation, there are three types, are written by xilinx Engineer, classical
Platform: | Size: 10240 | Author: 刘太联 | Hits:

[VHDL-FPGA-Verilog] READ

Description: 用于FPGA实现单总线测温电阻DS18b20时序。在xilinx spartan 3中试过。-failed to translate
Platform: | Size: 2048 | Author: chenxing | Hits:

[VHDL-FPGA-Verilog] 45561564

Description: 典型实例10.8 字符LCD接口的设计与实现 软件开发环境：ISE 7.1i 硬件开发环境：红色飓风II代－Xilinx版 1. 本实例控制开发板上面的LCD的显示； 2. 工程在\project文件夹里面 3. 源文件和管脚分配在\rtl文件夹里面 4. 下载文件在\download文件夹里面,.mcs为PROM模式下载文件,.bit为JTAG调试下载文件。-Typical examples of character LCD interface 10.8 The Design and Implementation of Software Development Environment: ISE 7.1i development environment hardware: Hurricane II on behalf of the red-Xilinx Edition 1. The above examples of the control board of the LCD display 2. Projects \ project folder inside 3. the distribution of the source file and pin in \ rtl folder inside 4. download files in \ download folder inside,. mcs file for the PROM mode download,. bit for the JTAG debugger to download the file.
Platform: | Size: 313344 | Author: 王磊 | Hits:
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